The PLL is widely applied in a System on Chip (SOC) to provide accurate and stable clock signal. FIG. 1 is a basic structure of a PLL, including a Phase Frequency Detector (PFD) 11, a Charge Pump (CP) 12, a Loop Filter (LP) 13, a Voltage Control Oscillator (VCO) 14 and a frequency divider 15.
The PFD 11 detects a frequency difference and a phase difference between a reference clock signal Fref and a feedback clock signal Ffb, and generates pulse control signals UP and DN and sends them to the CP 12. In the CP 12, the pulse control signals UP and DN are converted into current Ip so as to charge or discharge a capacitor Cp in the LP 13. The LP 13 generates and sends a control voltage Vctrl to the VCO 14. The VCO 14 increases an oscillation frequency of the clock signal Fout as the control voltage Vctrl is increased, and the VCO 14 decreases the oscillation frequency of the clock signal Fout as the control voltage Vctrl is decreased. An output clock signal Fout of the VCO 14 generates the feedback clock signal Ffb via the frequency divider 15. Thus, the above devices form a feedback system. When the frequency and phase of the output clock signal Fout are locked to a fixed frequency and phase. The PLL is in a lock status.
The accuracy and stability of the output clock signal of the PLL directly affects an operation of a next stage circuit in SOC. Thus, the lock detector for detecting the lock status of the PLL is necessary. When the PLL is in the lock status, the lock detector outputs a valid lock signal (such as digital signal 1) to the next stage circuit so as to activate the next stage circuit.
A conventional lock detector counts the reference clock signal and the feedback clock signal during a time period. If the counting value of the reference clock signal during the time period is equal to that of the feedback clock signal, the lock detector outputs a valid lock signal. This lock detector has a simple structure but can not reflect the lock status of PLL accurately. Because the feedback clock signal may not be stabilized (fast or slow) before the PLL is locked, it is possible that the lock detector can not obtain the lock status correctly. If the time period is short, it is possible that the counting value of the reference clock signal during the time period is equal to that of the feedback clock signal though the output clock signal of the PLL is not stable. Thus, the lock status is detected erroneously. In order to accurately detect the lock status of the PLL, the time period is configured to long enough. However, even the output clock signal is already stabilized, the next stage circuit will be activated after the time period elapses. Hence, the lock status of the PLL can not be detected in time.
Another conventional lock detector compares the phases of the reference clock signal with the feedback clock signal. When the phase difference between the reference clock signal and the feedback clock signal is within a predetermined range (such as 500 ps-1000 ps), a valid lock signal is output. However, this lock detector may also detect the lock status erroneously due to the unstable feedback clock signal. Moreover, due to the large frequency division factor of the frequency divider and the affection of the charging or discharging current of the CP, the jitter of the VCO is accumulated. Thus, it is possible that the phase difference between the reference clock signal and the feedback clock signal goes beyond the predetermined range even the output clock signal is stabilized.
Detailed descriptions regarding other structures of lock detectors for PLL are disclosed in other documents such as U.S. Pat. No. 6,320,469 and Chinese patent application No. 200580006798.X.